In digital communications, information is transferred between two terminals in the form of binary numbers. The terminals can be two electronic devices, such as a personal computer and a printer. The information can be transferred over a parallel bus, such as in a parallel output port of the personal computer, or over a serial connection, such as a Universal Serial Bus (USB) connection, which is now widespread.
The serial digital information transfer is particularly important for digital communications, because it can serve as an interface between digital systems employing different bit widths and internal communication protocols. Nowadays, disk drives in a personal computer frequently use a serial, not a parallel, connection to the mainframe board. This serial connection can be very fast due to high-speed serial communication enabled by serializer-deserializer (SERDES) integrated circuits. Furthermore, serial digital communication also allows one to use a single carrier (such as a coaxial cable or an optical fiber) for digital information transfer over large distances.
In serial digital communications, the information-carrying signal can be provided with or without a separate clock signal. In systems without the separate clock signal, the receiving circuitry generates an internal clock signal based on transitions between “one” and “zero” levels in the received serial digital signal itself. When the serial digital signal is not very stable in bit frequency or phase, the receiving circuitry may have a difficulty in correctly establishing the internal clock signal. Similarly, when a timing variation is present between the clock and the data signals in systems employing a separate clock signal, the receiving circuitry may have a difficulty in interpreting the received bits as ones or zeroes.
The timing variation of the digital binary signal, either with respect to a clock signal, or with respect to an “ideal” stable signal, is known as jitter. Jitter is commonly present in digital communications systems. Stability with respect to jitter is a very important characteristic of any electronic component or module employing serial or parallel digital communications.
Various standards with respect to tolerable levels of jitter have been developed. The digital communication components and modules need to be tested against these jitter standards. To test stability of electronic components with respect to jitter, a jittered clock reference signal, having a pre-defined amount of jitter, is required.
Cranford et al. in U.S. Pat. No. 7,512,177, incorporated herein by reference, discloses a jittered signal generator including a pulse generator coupled to a phase shifter. The phase shifter includes a plurality of quarter-wavelength lines having electrically variable capacitors. The capacitors are controlled by an arbitrary waveform generator. In operation, the arbitrary waveform generator causes the phase shifter to introduce a pre-defined, time-dependent amount of phase shift into the signal generated by the pulse generator, which introduces a pre-determined amount of jitter.
Frisch in U.S. Pat. No. 7,171,601, incorporated herein by reference, discloses a jitter generator based on a controllable delay line. Referring to FIG. 1, a jitter generator 10 includes a multiplexer 12, a programmable delay circuit 14, a programmable pattern generator 16, and a delay measurement unit 18. In a normal operating mode of the jitter generator 10, the multiplexer 12 delivers an input (“VIN”) signal to the delay circuit 14, and the delay circuit 14 delays the VIN signal by varying amounts of time to produce a jittery “TEST” signal. Clocked by a jitter clock signal JCLK, the pattern generator 16 supplies a sequence of digital “DELAY” words to the delay circuit 14, and each successive DELAY word controls a delay of the delay circuit 14. With the pattern generator 16 programmed to produce a suitable DELAY data sequence, the jitter generator 10 can produce a jittery TEST signal having a variety of jitter frequencies and amplitudes.
Jittered signal generators of the prior art commonly suffer from a drawback of complexity. By way of example, the multiplexor 12, the programmable delay circuit 14, the programmable pattern generator 16, and a delay measurement unit 18 of the prior-art jitter generator 10 of FIG. 1 can occupy a significant area on a printed circuit board.
The prior art is lacking a jittered signal generator that would be compact, simple, and inexpensive to implement. It is desirable that a jittered signal generator have a small number of electronic modules, for example two or even one module. The present invention provides such a solution.